Hdl
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Active-HDL v.8. 3. 2026
Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator.
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HDL Works HDL Companion v.2 4
HDL Companion is the HDL designer's Swiss army knife. It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources.
FIR HDL Writer v.0.9
FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's.
Wave VCD Viewer v.1.0.0.1
Wave VCD viewer is designed to bring digital design simulation results to your desktop PC. In a digital design environment the HDL designs are typically simulated in EDA workstations.
Atmel IDS v.6.0
A tool for creating fast, predictable designs with ATA6625 AT40K, AT40KAL, and AT6000 series FPGAs using HDL Planner for VHDL and Verilog Entry. This tool can be used with other popular synthesis tool environments.
AntiChoresterol Diet v.1.0.0.0
Cholesterol is a sterol (a lipid) found in the blood (blood plasma) and tissues, two types of cholesterol, the good (HDL)and bad (LDL). Bad cholesterol is concentrated as a residue on the walls of the arteries blocking the free flow of blood, where
Elphel reconfigurable cameras v.353.8.0.9
Software and HDL code for Elphel reconfigurable network cameras
HDLObf v.1.0
HDLObf is intended to be a HDL Obfuscator and identifier name change utility.
Icarus Verilog v.0.9.5
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
MB Cholesterol Risk Calculator
MB Free Cholesterol Risk Calculator is a simple health software with an easy to use interface. The program is designed to calculate the risk of a person suffering from a heart attack in the next ten years depending on cholesterol levels and their effects.
DSP Builder v.8 1
DSP Builder technology allows you to go from system definition/simulation using the industry-standard The MathWorks/Simulink tools to system implementation in a matter of minutes. The DSP Builder Signal Compiler block reads Simulink Model Files (.